The present invention relates to a technique of semiconductor integrated circuit (device) and particularly to the technique which may be effectively applied to the semiconductor integrated circuit device including a bipolar device and a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on one chip.
The semiconductor integrated circuit device is formed of various circuits and introduces a so-called Bi-CMOS circuit combining a bipolar transistor which assures high-speed operation property and a complementary MISFET which assures low power consumption.
Particularly, development of communication technology requires a semiconductor integrated circuit which ensures high-speed operation rate for wider frequency range.
For example, a CDR (Clocked Data Recovery) circuit for processing a high-speed signal is described in the ISSCC 2000 Digest of Technical Papers (Feb. 7, 2000) p. 57. As illustrated in FIG. 3.4.1 of this reference, a signal is outputted by synchronizing a high-speed input signal (Data input) with the clock signal generated by a VOC (Voltage-controlled Oscillator) circuit.
Moreover, the Japanese Unexamined Patent Publication No. Hei 6(1994)-237160 discloses the technique related to a multiplexer using Bi-CMOS, a logical gate, and an adder.